Field-controlled high-power semiconductor devices

ABSTRACT

Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. The top semiconductor layer forms a control layer ( 60 ). A semiconductor layer junction, remote from both device surfaces, forms a blocking p-n junction ( 54 ) capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region ( 64 ) extending from the top surface into the control layer ( 60 ). A conductive tub region ( 62 ), spaced apart from the top conductive region ( 64 ), extends from the top surface at least through the control layer ( 60 ). A field effect region ( 80 ) is disposed in the control layer ( 60 ) between the top conductive region ( 64 ) and tub region ( 62 ). A gate contact ( 18 ) is formed over the field effect region ( 80 ) causing the creation and interruption of a conductive channel ( 82 ) between the top conductive region ( 64 ) and conductive tub region ( 62 ) so as to turn the device on and off.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. application Ser. No.09/095,481 filed Jun. 10, 1998, now U.S. Pat. No. 6,107,649, Issued Aug.22, 2000.

TECHNICAL FIELD

This invention relates to power semiconductor devices, and moreparticularly relates to power semiconductor devices in which a p-njunction, remote from the device surfaces, carries the device operatingvoltage and field effect gates are used to control the device operation.

BACKGROUND ART

Power semiconductors, as distinguished from signal semiconductors, areused to process and control the flow of electric energy supplied to userloads. The utility of such devices is driven by their ability to quicklyand efficiently switch on and off large operating voltages and currents.Power semiconductor switching devices are increasingly being designed tohandle applications requiring high blocking voltages in the offcondition, typically 1 kV and greater, and high current requirements inthe on state, typically 1 A and greater. Recent advances in deviceoperating thresholds, however, have imposed operational andfabrication-related problems for power semiconductor devices.

Historically, power semiconductor devices have required large switchingcurrents to handle the corresponding high device currents. Largeswitching currents result in device inefficiencies since excessiveelectrical power is required to operate the device. Power semiconductordevices to-date have employed metal-oxide-semiconductor (MOS) gatestructures in a variety of arrangements to achieve the low currentturn-on and turn-off requirements of these devices. However, MOS gateshave experienced operational and fabrication-related reliabilityproblems as the operational boundaries of the power semiconductordevices have been expanded. In particular, the high operating devicevoltages create large electric fields within these devices, which poseslong-term reliability problems for the oxides used in the MOS gates.Trenched MOS gates (UMOS), as found in the paper by A. K. Agarwal et al.entitled SiC Power Device Development given at the All Electric CombatVehicle (AECV) Second International Conference Jun. 8th-12th 1997, andburied structures, U.S. Pat. No. 5,543,637, have been employed topartially overcome these oxide limitations. In each of thesearrangements, however, large electric fields are still present at theoxide interfaces thereby compromising the long-term oxide reliability.Finally, gate oxides are often fabricated on implanted semiconductorregions, which results in low oxide quality and reliability,particularly in power devices fabricated from SiC. An exemplaryhigh-power thyristor device employing such a MOS gate structure can befound in the above article by A. K. Agarwal.

The need exists for monolithic, simply constructed, easily fabricated,power semiconductor devices in which the controlling gate structures arefabricated without oxides or dielectric insulators and are removed fromthe large electric fields within the device. Although non-oxide gatestructures are preferred, the need also exists to provide a reliable,non-implanted semiconductor surface on which to fabricate gate oxides,for those power semiconductors which continue to employ MOS gates, andto isolate such gate oxide from the large electric field stresses.

SUMMARY OF THE INVENTION

A preferred embodiment according to the present invention provides for asemiconductor device comprising: (a) a semiconductor structure havingtop and bottom surfaces, the structure including a plurality ofsemiconductor layers defining a blocking p-n junction remote from boththe surfaces, the structure including a control layer defining the topsurface of the structure; a top conductive region extending from the topsurface; a conductive tub region spaced apart from the top conductiveregion and extending from the top surface toward the blocking p-njunction at least through the control layer, the control layer includinga field effect region disposed between the top conductive region and theconductive tub region; (b) a top ohmic contact in contact with the topsurface at the top conductive region; (c) a bottom ohmic contact incontact with the semiconductor structure below the blocking p-njunction, the semiconductor layers being arranged so that when apotential is sustained between the top and bottom ohmic contacts, amajor portion of the potential appears across the blocking p-n junctionthereby forming depletion regions about the blocking p-n junction, and(d) a gate contact overlying the field effect region, wherebyconductivity of the field effect region can be selectively controlled bya controlling potential on the gate contact to create and interrupt aconductive channel within the control layer, the top conductive regionand the conductive tub region being coupled and decoupled by theconductive channel, the conductive tub region extending downwardly tothe vicinity of the blocking p-n junction so that a least resistivecurrent path including the top conductive region, the conductive channeland the conductive tub region is created between the top ohmic contactand the blocking p-n junction when the conductive channel is created.

In yet another embodiment, the semiconductor device further comprises acontrol p-n junction disposed above the blocking p-n junction and remotefrom the top surface, the gate contact forming a Schottky contact suchthat the gate contact, the field effect region, the top conductiveregion and the conductive tub region constitute a MESFET. Alternatively,the semiconductor device may further comprise a control p-n junctiondisposed above the blocking p-n junction and remote from the topsurface, the field effect region having a gate conductive regionextending from the top surface under the gate contact toward the controlp-n junction such that the gate contact, the gate conductive region, thefield effect region, the top conductive region and the conductive tubregion constitute a JFET. Alternatively, the semiconductor device mayfurther comprise a control p-n junction disposed above the blocking p-njunction and remote from the top surface, the gate contact including aninsulative layer on the top surface and a conductive contact on theinsulative layer such that the gate contact, the field effect region,the top conductive region and the conductive tub region constitute aMOSFET. Yet another embodiment includes the semiconductor device inwhich the top conductive region includes a first subregion of samesemiconductor type as the control layer and extending to a first depthfrom the top surface, a second subregion of opposite semiconductor typefrom the control layer extending to a second depth from the top surfaceand disposed between the first subregion and the field effect region,both of the subregions being in contact with the top ohmic contact, thegate contact including an insulative layer on the top surface and aconductive contact on the insulative layer such that the gate contact,the field effect region, the second subregion of the top conductiveregion and the conductive tub region constitute a MOSFET.

Additional embodiments of the invention include the semiconductor devicein which the field effect region includes unimplanted epitaxially grownsemiconductor defining the top surface in the field effect region,whereby the insulative layer includes an insulating compound on theunimplanted epitaxially grown semiconductor.

In one preferred embodiment, the semiconductor device may also bearranged such that the semiconductor device is a field controlledtransistor, the conductive tub region extending at least to the blockingp-n junction and having a bottom end being disposed in the depletionregion of the blocking p-n junction when the potential is sustainedbetween the top and bottom ohmic contacts, the conductive tub regionbeing alternatively depleted and undepleted of carriers in response tothe selective controlling potential on the gate contact, whereby thetransistor switches “off” and “on” respectively. In this embodiment thesemiconductor device may have the top conductive region including afirst subregion of same semiconductor type as the control layer andextending to a first depth from the top surface; a second subregion ofopposite semiconductor type from the control layer extending to a seconddepth from the top surface and disposed between the first subregion andthe field effect region, both subregions in contact with the top ohmiccontact, the gate contact including an insulative layer on the topsurface and a conductive contact on the insulative layer such that thegate contact, the field effect region, the second subregion of the topconductive region and the conductive tub region constitute a MOSFET.Alternatively, the semiconductor device further comprises a control p-njunction disposed above the blocking p-n junction and remote from thetop surface, the gate contact forming a Schottky contact such that thegate contact, the field effect region, the top conductive region and theconductive tub region constitute a MESFET. Alternatively, thesemiconductor further comprises a control p-n junction disposed abovethe blocking p-n junction and remote from the top surface, the fieldeffect region having a gate conductive region extending from the topsurface under the gate contact toward the control p-n junction such thatthe gate contact, the gate conductive region, the field effect region,the top conductive region and the conductive tub region constitute aJFET. In yet other preferred embodiments, the semiconductor devicecomprises a control p-n junction disposed above the blocking p-njunction and remote from the top surface, the gate contact including aninsulative layer on the top surface and a conductive contact on theinsulative layer such that the gate contact, the field effect region,the top conductive region and the conductive tub region constitute aMOSFET.

In an additional preferred embodiment is provided the semiconductor inwhich the semiconductor device is a field-gated bipolar transistor, thesemiconductor structure having a lower p-n junction remote from the topand bottom surfaces and disposed below the blocking p-n junction, theconductive tub region extending at least to the blocking p-n junctionand having a bottom end being disposed in the depletion region of theblocking p-n junction when the potential is sustained between the topand bottom ohmic contacts, the conductive tub region being alternativelydepleted and undepleted in response to the selective controllingpotential on the gate contact, whereby the bipolar transistor switches“off” and “on” respectively. This embodiment may further include asemiconductor device in which the top conductive region includes a firstsubregion of same semiconductor type as the control layer and extendingto a first depth from the top surface, a second subregion of oppositesemiconductor type from the control layer extending to a second depthfrom the top surface and disposed between the first subregion and thefield effect region, both subregions in contact with the top ohmiccontact, the gate contact including an insulative layer on the topsurface and a conductive contact on the insulative layer such that thegate contact, the field effect region, the second subregion of the topconductive region and the conductive tub region constitutes a MOSFET. Inanother variation, the semiconductor device may further comprise acontrol p-n junction disposed above the blocking p-n junction and remotefrom the top surface, the gate contact forming a Schottky contact suchthat the gate contact, the field effect region, the top conductiveregion and the conductive tub region constitute a MESFET. In yet anothervariation, the semiconductor device further comprised a control p-njunction disposed above the blocking p-n junction and remote from thetop surface, the field effect region having a gate conductive regionextending from the top surface under the gate contact toward the controlp-n junction such that the gate contact, the field effect region, thegate conductive region, the top conductive region and the conductive tubregion constitute a JFET. In a final variation of this type, thesemiconductor device further comprises a control p-n junction disposedabove the blocking p-n junction and remote from the top surface, thegate contact including an insulative layer on the top surface and aconductive contact on the insulative layer such that the gate contact,the field effect region, the top conductive region and the conductivetub region constitute a MOSFET.

In an additional preferred embodiment is provided the semiconductordevice in which the semiconductor device is a field turn-off thyristor;(a) the top conductive region including a first subregion extending to afirst depth from the top surface, and a second subregion extending to asecond depth from the top surface and disposed between the firstsubregion and the field effect region, both subregions in contact withthe top ohmic contact; (b) the semiconductor structure having a lowerand an upper p-n junction, both remote from the top and bottom surfaces;the lower p-n junction disposed below the blocking p-n junction, theupper p-n junction disposed above the blocking p-n junction, theconductive tub region extending at least through the upper p-n junction;a latch-on gate ohmic contact overlying the conductive tub region at thetop surface, whereby when the conductive channel is interrupted, currentflow through the conductive tub region can be selectively controlled bya controlling current applied through the latch-on gate ohmic contact toturn on the upper p-n junction and thereby switch “on” the thyristor;and whereby in an absence of the controlling current on the latch-ongate contact, the controlling potential on the gate contact can createthe conductive channel to bypass the upper p-n junction and therebyswitch “off” the thyristor. In one variation, the semiconductor devicehas the first subregion of same semiconductor type as the control layer,the second subregion is of opposite semiconductor type from the controllayer, the gate contact including an insulative layer on the top surfaceand a conductive contact on the insulative layer such that the gatecontact, the field effect region, the second subregion of the topconductive region and the conductive tub region constitute a MOSFET. Inanother variation, the semiconductor device further comprises a controlp-n junction disposed above the upper p-n junction and remote from thetop surface, the first subregion being of opposite semiconductor typefrom the control layer, the second subregion of same semiconductor typeas the control layer, the first depth of the first subregion extendingbeyond the control p-n junction from the top surface, the gate contactforming a Schottky contact such that the gate contact, the field effectregion, the second subregion of the top conductive region and theconductive tub region constitute a MESFET. In yet another variation, thesemiconductor device further comprises a control p-n junction disposedabove the upper p-n junction and remote from the top surface, the firstsubregion being of opposite semiconductor type from the control layer,the second subregion of same semiconductor type as the control layer,the first depth of the first subregion extending beyond the control p-njunction from the top surface, the field effect region further comprisesa gate conductive region extending from the top surface under the gatecontact toward the control p-n junction such that the gate contact, thefield effect region, the gate conductive region, the second subregion ofthe top conductive region and the conductive tub region constitute aJFET. In a final variation of this type, the semiconductor devicefurther comprises a control p-n junction disposed above the upper p-njunction and remote from the top surface, the first subregion being ofopposite semiconductor type from the control layer, the second subregionof same semiconductor type as the control layer, the first depth of thefirst subregion extending beyond the control p-n junction from the topsurface, the gate contact including an insulative layer on the topsurface and a conductive contact on the insulative layer such that thegate contact, the field effect region, the second subregion of the topconductive region and the conductive tub region constitute a MOSFET.

In additional embodiments of the invention, the semiconductor deviceincludes a semiconductor structure further comprising a blocking layerof relatively low doping concentration disposed below the blocking p-njunction and an enhancement layer of same semiconductor type andrelatively higher doping concentration as the blocking layer disposedabove the lower p-n junction. Also, the semiconductor device may havethe top conductive region including a first subregion of oppositesemiconductor type from the control layer and extending through thecontrol p-n junction from the top surface, and a second subregion of thesame semiconductor type as the control layer extending to a second depthfrom the top surface and disposed between the first subregion and thefield effect region, both of the subregions in contact with the topohmic contact. The semiconductor device may also have semiconductorlayers composed of a material selected from the group consisting of SiC,Si, Diamond, GaAs, GaN, AlN, AlGaN, InGaN, GaP, AlGaP or AlGaAsP andcombinations thereof Additionally, the semiconductor device includessemiconductor layers including a bottom layer, the bottom layer being incontact with the bottom ohmic contact and further including a bufferlayer for improving the semiconductor structure quality.

In yet additional embodiments, the semiconductor device has noinsulative layer as part of the gate contact. Also, the semiconductormay further comprise a control p-n junction disposed above the blockingAn junction and remote from the top surface, the field effect regionincluding an unimplanted portion of the control layer. Also, thesemiconductor device may further comprise a control p-n junctiondisposed above the blocking p-n junction and remote from the topsurface; an upper p-n junction disposed between the blocking p-njunction and the control p-n junction. Additionally, the semiconductordevice further comprises a lower p-n junction disposed below theblocking p-n junction and remote from the bottom surface. Also, thesemiconductor device has the top conductive region including a firstsubregion of opposite semiconductor type from the control layerextending to a first depth at least through the control layer from thetop surface; a second subregion of the same semiconductor type as thecontrol layer extending to a second depth not through the control layerfrom the top surface and disposed between the first subregion and thefield effect region, the first and second subregions being in contactwith the top ohmic contact.

In other embodiments, the semiconductor device has the top conductiveregion including a first subregion of same semiconductor type as thecontrol layer extending to a first depth not through the control layerfrom the top surface; a second subregion of opposite semiconductor typefrom the control layer and extends to a second depth, shallower than thefirst depth, from the top surface and disposed between the firstsubregion and the field effect region, both subregions being in contactwith the top ohmic contact. Also, the semiconductor device may have theconductive tub region extending at least to the blocking p-n junctionand has a bottom end disposed in the depletion region of the blockingp-n junction when the potential is sustained between the top and bottomohmic contacts such that the field effect region is shielded from thepotential. The semiconductor device may also further comprise a latch-ongate ohmic contact overlying the conductive tub region at the topsurface. Additionally, the semiconductor device may further comprise alower and an upper p-n junction, both remote from the top and bottomsurfaces, the lower p-n junction disposed below the blocking p-njunction, the upper p-n junction disposed above the blocking p-njunction, the conductive tub region extending through the upper p-njunction; a latch-on gate ohmic contact overlaying the conductive tubregion at the top surface, the semiconductor layers being of relativeconductivity, whereby a latch-on current applied at the latch-on gateohmic contact, flows through the conductive tub region and laterallybeneath the upper p-n junction before traversing the upper p-n junctionbeneath the top ohmic contact.

In yet another embodiment of the present invention, the semiconductordevice further comprises a semi-insulating layer disposed directlybeneath the control layer and the field effect region; the conductivetub region extending at least through the semi-insulating layer, wherebythe field effect region within the control layer is electricallyisolated by the semi-insulating layer from a semiconductor layerdirectly beneath the semi-insulating layer in a direction perpendicularto the top surface. In variations in this embodiment, the semiconductordevice may include the gate contact forming a Schottky contact such thatthe gate contact, the field effect region, the top conductive region andthe conductive tub region constitute a MESFET, or the field effectregion further including a gate conductive region extending from the topsurface under the gate contact toward the semi-insulating layer suchthat the gate contact, the gate conductive region, the field effectregion, the top conductive region and the conductive tub regionconstitute a JFET.

Further embodiments of the invention include the semiconductor device inwhich the conductive tub comprises a part of a blocking layer defining alower semiconductor layer of the blocking p-n junction, or thesemiconductor device in which the conductive tub comprises a part of thecontrol layer, or the semiconductor device in which the conductive tubcomprises an ion implanted region. extending from the top surface.

In a preferred method of the present invention, a method is provided foroperating a semiconductor device having a plurality of semiconductorlayers, a top and bottom surface and including a control layer definingthe top layer of the device, the method comprising the steps of: (a)applying a voltage between a top and a bottom ohmic contact of thesemiconductor device; (b) sustaining the voltage across a blocking p-njunction defined by the semiconductor layers and remote from the top andbottom surfaces; (c) selectively creating or interrupting a conductivechannel in the control layer between a top conductive region, disposedbelow the top ohmic contact, and a tub conductive region, spaced apartfrom the top conductive region and extending at least to the blockingp-n junction, by applying a control potential to a gate contact disposedover the control layer so as to cause a least resistive path includingthe top conductive region, the conductive channel and the conductive tubregion to be created between the top ohmic contact and the blocking p-njunction when the conductive channel is created.

In another preferred method, a method is provided for operating asemiconductor device having a plurality of semiconductor layers, a topand bottom surface and including a control layer defining the top layerof the device, the method comprising the steps of: (a) applying avoltage between a top and a bottom ohmic contact of the semiconductordevice; (b) sustaining the voltage across a blocking p-n junctiondefined by the semiconductor layers and remote from the top and bottomsurfaces; (c) selectively applying a control current to a latch-on gatecontact disposed over a tub conductive region, the tub conductive regionextending through an upper p-n junction defined by the semiconductorlayers and remote from the top and bottom surfaces, the upper p-njunction being disposed above the blocking p-n junction and beingselectively turned on when the control current is selectively applied tothe latch-on gate; (d) selectively creating or interrupting a conductivechannel in the control layer between a top conductive region, disposedbelow the top ohmic contact, and a tub conductive region, spaced apartfrom the top conductive region and extending through the upper p-njunction, by applying a control potential to a gate contact disposedover the control layer so as to selectively short-circuit the upper p-njunction when the conductive channel is created thereby turning off thethyristor semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view of the multilayer wafer of a full powersemiconductor device embodying one form of the invention.

FIG. 1B is a side view of the wafer of FIG. 1A with applied controlsources attached.

FIG. 2A is an enlarged sectional view of a single field turn-offthyristor cell along line 2—2 of FIG. 1.

FIGS. 3A, 4A and 5A are enlarged sectional views of additionalembodiments of the invention of FIG. 2A.

FIGS. 2B, 3B, 4B and 5B depict enlarged, more detailed views of portionof FIGS. 2A, 3A, 4A and 5A respectfully.

FIGS. 6A, 7, 8 and 9 are enlarged sectional views of field-controlledtransistors according to further embodiments of the invention.

FIGS. 6B and 6C depict enlarged, more detailed views of alternativeembodiment of portions of FIG. 6A, 7, 8, 10, 11 and 12 according to thepresent invention.

FIGS. 10-13 are enlarged sectional views of field-gated bipolartransistor cells according to further embodiments of the invention.

FIGS. 14A and 15A are further embodiments of an enlarged sectional viewof a single field turn-off thyristor cell along line 2—2 of FIG. 1.

FIGS. 14B and 15B depict enlarged, more detailed views of portion ofFIGS. 14A and 15A respectfully.

FIGS. 16 and 17 are enlarged sectional views of field-gated bipolartransistors according to further embodiments of the invention.

FIGS. 16B and 17B are alternative embodiments of the field effect regionof FIGS. 16 and 17 respectively.

FIGS. 18 and 19 are enlarged sectional views of field-controlledtransistors according to further embodiments of the invention.

BEST MODE OF CARRYING OUT THE INVENTION

Referring to FIGS. 1A and 1B, in accordance with one embodiment of theinvention a power semiconductor device 8 consists of a thinsemiconductor wafer 10 comprised of multiple semiconductor layersextending through the wafer. Wafer 10 is bounded by top device surface11 and bottom device surface 13. The device includes top ohmic contact12 and bottom ohmic contact 16 for connection to external applied devicevoltage 14. Interdigitated gate contact 18, top ohmic contact 12 andthyristor turn-on gate contact 20 are formed on the top surface 11.Thyristor turn-on contact is only necessary for the thyristor typedevices described below. External applied gate voltage is shown at 22and external biasing current source at 23. Alternative geometries andlayouts for the device contacts 12, 18 and 20 are also feasible. Wafer10 is preferably made of SiC, although alternative semiconductormaterials capable of both p-type and n-type doping, including but notlimited to SiC, Si, Diamond, GaAs, GaN, AlN, AlGaN, InGaN, GaP, AlGaP orAlGaAsP, may be used. Peripheral edge termination rings 19, or otheredge termination structures, may also be used.

FIG. 2A represents a single section or “cell” 40 of wafer 10 as seenthrough section 2—2 of FIG. 1A. In particular, cell 40 of FIG. 2 is apower thyristor made of SiC according to one preferred embodiment of theinvention. It should be appreciated that wafer 10 includes numerouscells 40 of the type described. The semiconductor structure of FIG. 2Aincludes a bottom layer n+ substrate 42. The doping concentration ofsubstrate 42 is typically 1×10¹⁹/cm³ or greater. Substrate 42 is also incontact with bottom ohmic contact 16 (thyristor cathode) at bottomdevice surface 13. An optional, relatively thin n+ buffer layer 44, of0.5 gm for example, may be epitaxially grown on the upper surface ofsubstrate 42 to improve the quality of subsequently grown semiconductorlayers. Buffer layer 44 is typically used as a bed upon which subsequentsemiconductor layers of high crystalline quality are epitaxially grownwhen substrate 42 is cut from a bulk source. Buffer layer 44 has adoping concentration similar to that of substrate 42.

P-blocking layer 46 is epitaxially grown on buffer layer 44 to formlower p-n junction 48. Blocking layer 46 is relatively thick and lightlydoped as compared to substrate 42. Blocking layer 46 optionally includesp doped intermediate layer 50 adjacent to either substrate 42 oroptional buffer layer 44. Intermediate layer 50 is epitaxially grownprior to blocking layer 46 and is more heavily doped than blocking layer46. Intermediate layer 50 is typically included to create an asymmetricdevice having a more uniformly distributed electric field in blockinglayer 46 under forward-biased applied device voltage 14. An n-typeconduction layer 52 is epitaxially grown on blocking layer 46 to formblocking p-n junction 54. Conduction layer 52 is thinner and has agreater doping concentration than blocking layer 46. Depletion regions56 are formed in conduction layer 52 and blocking layer 46. The higherdoping concentration of conduction layer 52 vis-a-vis blocking layer 46results in a significantly larger depletion region 56 within blockinglayer 46 than in conduction layer 52.

P anode layer 58 is epitaxially grown on conduction layer 52 formingupper p-n junction 59. Anode layer 58 should have a thickness and dopinglevel such that its intralayer conductivity, i.e. parallel to top andbottom surfaces 11 and 13 and parallel to upper p-n junction 59, is muchlower than that of conduction layer 52. N-type control layer 60 isepitaxially grown on anode layer 58 forming control p-n junction 61. Itshould be appreciated that the doping concentration and thickness ofcontrol layer 60 are variable in determining both the maximum range ofexternally applied gate voltage 22 used to switch semiconductor device 8off and the maximum current to be controlled through top contact 12.Further, the doping concentration and thickness of control layer 60 alsodetermine the “normally-on” or “normally-off” status of the gateoperation over the field effect region as described below. Othersemiconductor growth methods may also be used to form any one or more ofsemiconductor layers described above.

N+ conductive tub region 62, and top conductive region 64, are createdby ion implantation into control layer 60. More particularly, theseregions are preferably created by triple ion implantation consisting ofa first implantation to create n+ tub 62 a second implementation tocreate n+ first subregion 66, and a third implantation to create p+second subregion 68. Alternatively, first subregion 66 and tub region 62can be created during a single ion implantation step by using asacrificial mask layer on top of first subregion 66. The n+ implantationcan be performed using any n-type dopant although nitrogen is preferred.The p+ implantation can be performed using any p-type dopant, aluminumor boron for example, although a carbon/aluminum sequential,co-implantation employing approximately equal ion concentrations ofcarbon and aluminum is preferred. In a preferred implantation method,n-type nitrogen implantation is performed at a temperature greater than600 degrees Celsius, and carbon/aluminum co-implantation is performed atroom temperature. Photolithographic processes may be used to define theboundaries of the implanted regions. Post implantation annealing for allimplanted regions, 62, 66 and 68 is performed at a common temperature ofapproximately 1200-1600 degrees Celsius for 10-60 minutes, althoughindividual annealing of each implanted region may also be practiced.

On-gate contact 20 and top ohmic contact 12 are created after postimplantation annealing by depositing an n-type ohmic contact refractorymetal, alloy or high temperature silicide onto top surface 11 overn-type subregion 66 and tub region 62. Similarly, top ohmic contact 12is created by depositing a p-type ohmic contact refractory metal, alloyor high temperature silicide onto device top surface 11 over p-typesubregion 68. Preferred materials for the ohmic contact on the p-typeregions include titanium, whereas preferred ohmic contact materials forthe n-type regions include nickel. The ohmic contacts are then annealedat a temperature of 800 to 1300 degrees Celsius, although a preferredannealing occurs at a temperature of 900-1100 degrees Celsius for aduration of up to 60 minutes. Although not shown in FIG. 2A, additionalstandard semiconductor manufacturing practices may be used, includingbut not limited to the use of field oxide, passivation oxide, guard ringedge termination, field plates and p-n junction extensions.

Gate contacts 18 are created by one of a variety of methods depending onthe type of gate structure desired. In the case of the Schottky gatecontact 18 of FIG. 2A, gate metals that form high Schottky barrierheights, such as platinum, palladium and gold are preferred. A finalgate metalization is used to deposit photolithographically defined gatecontact 18. As further shown in FIG. 2B, a metal-semiconductor fieldeffect transistor (MESFET) 69, having first subregion 66 of the topconductive region as the source and tub region 62 as the drain, resultsfrom the creation of a Schottky barrier gate over field effect region 80of control layer 60.

The field turn-off thyristor (FTO) of FIGS. 2A and 2B operates byapplying external device voltage 14 between thyristor top ohmic (anode)contact 12 and thyristor bottom ohmic (cathode) contact 16. For thedevice shown in FIGS. 2A and 2B, the required external device voltage 14results in anode 12 being positively with respect to cathode 16, and thethyristor is forward-biased. In this state, the upper and lower p-njunctions, 59 and 48 respectively, are also both forward-biased.Further, blocking junction 54 is reverse-biased in this configurationand sustains the applied external device voltage between the anode andcathode when the thyristor is in the “off” state. The differences in therelative doping concentration and thickness of blocking layer 46 ascompared to heavier doped conductive layer 52 cause most of appliedexternal device voltage 14 to be sustained across reverse-biasedblocking junction 54. As with control layer 60, the dopingconcentrations and thicknesses of blocking layer 46 and conduction layer52 should be controlled during device fabrication so as to accommodatethe desired applied device voltages 14 to achieve proper thyristoroperation. In particular, since blocking layer 46 is more lightly dopedthan conduction layer 52, depletion region 56 in blocking layer 46 isproportionately larger and extends farther into blocking layer 46 thaninto conduction layer 52, as shown in FIG. 2A.

In addition to external device voltage 14, the gate bias voltage 22 ofFIG. 1B is applied between anode contact 12 and gate contact 18. Priorto thyristor turn-on, applied gate bias voltage 22 should cause fieldeffect region 80 in control layer 60 of MESFET 69 to be devoid ofcarriers down to depletion boundary 83 which touches control p-njunction 61 (hereafter referred to as “pinched off”). “Pinch off” offield effect region 80 creates a high impedance path between firstsubregion 66 of top conductive region 64 and tub region 62. As mentionedabove, the doping concentration and thickness of control layer 60 affectthe gate bias voltage needed for “pinch-off”. At a gate bias voltage 22of 0V, for example, sufficiently thin and lightly doped control layer 60will enable the more shallow built-in depletion boundary 84 to touchcontrol junction 61 and “pinch off” field effect region 80, therebycreating a “normally-off” conduction channel in the FTO device.Alternatively, a thicker and more heavily doped control layer 60 willresult in the need for a non-zero gate bias voltage 22 to be applied togate 18 in order to “pinch-off” field effect region 80, thereby creatinga “normally on” field-controlled, gate region.

An external, biasing current source (i.e. negative current) 23 isintroduced at turn-on gate 20 to turn the thyristor on. Under theforward bias applied device voltage 14, electron injection from turn-ongate 20 through tub region 62 and into conduction layer 52 occurs,effectively turning on forward-biased, upper p-n junction 59. Theturning on of upper p-n junction 59 leads to hole injection from anoderegion 68 and p anode layer 58. Since upper p-n junction 59 isforward-biased and the n-type conduction layer 52 is of higherconductivity than the p-type anode layer in a direction parallel todevice surfaces 11 and 13, holes are injected across upper p-n junction59 beneath p+ subregion 68 which results in the turn-on of the thyristorby the well-known regenerative process of hole injection from the anodeand election injection from the cathode.

After the thyristor has become conducting, it can be turned-off byapplying an external gate turn-off voltage 22 at gate contact 18.Assuming a normally off device within field effect region 80, MESFET 69operates under gate turn-off voltage 22 to reduce the depletion regionboundary 83 in field effect region 80 of control channel 60, therebycreating a low impedance conduction channel 82 coupling first subregion66 of top conductive region 64 and tub region 62. At a threshold gateturn-off voltage, this low impedance conduction channel provides a lowerresistive path for the anode current sufficient to shunt the currentfrom anode contact 12 through subregion 66, conduction channel 82,conductive tub region 62 and into conduction layer 52. This shunting ofcurrent from the anode is such that the current necessary to support thewell-known regenerative process of hole and electron injection isreduced below a threshold level. Therefore, the shunted current bypassesupper p-n junction 59, or alternatively, the upper p-n junction isshorted by the conduction of current through the tub, and thus turnsthyristor 40 “off” by breaking the positive-feedback regenerativeprocess of carrier injection within the thyristor.

The thyristor devices of FIGS. 3A and 4A are fabricated and operated ina manner similar to the device of FIGS. 1 and 2, with the differencesbeing in the fabrication and operation of the gate structure at gatecontact 118. In the device of FIG. 3, a p+ ion implanted region 100 iscreated and extends into control layer 160 from top device surface 111between first subregion 166 and tub region 162. P+ region 100 isimplanted during a separate ion implantation process similar to thatused to create the p+ subregion 168 of top conductive region.Alternatively, p+ region 100 and second subregion 168 can be createdduring a single ion implantation step by using a sacrificial mask layeron top of p+ region 100. P-type metal gate contact 118 overliesimplanted region 100 and is created by depositing a p-type refractorymetal, alloy or high temperature silicide onto device top surface 111.Metal gate contact 118 is desirably formed during the formation of anodecontact 112 over p+ implanted subregion 168 and is annealed as discussedabove.

In FIG. 3B, a junction field effect transistor (JFET) 169, havingsubregion 166 of top conductive region as a source and tub region 162 asa drain, results from the deposit of gate contact 118 over implantedregion 100 within control layer 160. Prior to thyristor turn-on, anexternal applied gate voltage should cause field effect region 180 incontrol layer 160 of JFET 169 to be devoid of carriers down to depletionboundary 183 which touches control p-n junction 161 (i.e. “pinched-off”), effectively creating a high impedance path between first subregion166 and tub region 162. The doping concentrations and thicknesses ofcontrol layer 160 and implant region 100 affect the gate bias voltageneeded for “pinch-off” . At a gate bias voltage of 0V, for example,sufficiently thin and lightly doped control layer 160 enables built-indepletion boundary 184 beneath junction 110 to “pinch-off” field effectregion 180. During thyristor “turn-off”, JFET 169 operates to reduce thedepletion boundary 183 in field effect region 180 of control layer 160as a result of an external gate turn-off voltage applied at gate contact118, thereby creating a least resistive current shunting conductionchannel 182 coupling first conductive subregion 166 and tub region 162and effectively shorting the upper p-n junction.

The alternative thyristor gate structures in FIGS. 4A and 4B are formedby growing and photolithographically defining gate insulator 230 overcontrol layer 260 between first subregion 266 and tub region 262following the post-implantation annealing of regions 266, 268, and 262.Although other insulators may be used, the preferred gate insulator issilicon dioxide and the preferred growth method is thermal oxidationperformed at a temperature of 1100 to 1200 degrees Celsius. The durationof oxidation determines the final oxide thickness, preferably 400 to2000 angstroms. For oxide insulators greater than 1000 angstroms, thepreferred growth method is thermal growth of approximately 1000angstroms of oxide followed by chemical vapor deposition of theremaining oxide. Gate contact 218 is deposited during either the p-typeor n-type refractory metal deposition after the gate insulator has beendefined. A preferred gate contact growth method is to deposit dopedpolysilicon on gate insulator 230 prior to depositing metal for gatecontact 218. Annealing of all device contacts can be done as individuallayers are deposited, although it is preferred that all contactannealing be done contemporaneously. All of the gate insulator 230 ofFIGS. 4A and 4B is formed over epitaxially deposited control layer 260and is not subject to the large electric fields within the thyristor,which are sustained at blocking junction 254, thereby providing ahigh-quality, reliable gate insulator with high channel mobility freefrom excessive electric field stresses.

In the device of FIG. 4B, a depletion-mode metal-oxide-semiconductor(depletion-mode MOSFET) 269, having first subregion 266 of topconductive region as a source and tub region 262 as a drain, resultsfrom gate contacts 218 and insulative layers 230 being deposited overcontrol layer 260. Prior to thyristor turn-on, an external applied gatebias voltage should cause field effect region 280 in control layer 260of MOSFET 269 to be devoid of carriers down to depletion boundary 283which touches control junction 261 (i.e. “pinched-off”), therebycreating a high impedance path between first subregion 266 and tubregion 262. The doping concentration of control layer 260, thethicknesses of control layer 260 and oxide layer 230, as well as theworkfunction of gate metal 118 affect the gate bias voltage needed for“pinch-off”. At a gate bias voltage of 0V, for example, sufficientlythin and lightly doped control layer 260 enables built-in depletionboundary 284 to “pinch-off” field effect region 280. In this case, thegate structure may actually be considered an enhancement-mode MOSFET.During thyristor “turn-off”, MOSFET 269 operates to reduce the depletionboundary 283, in field effect region 280 of control layer 260 as aresult of an external gate turn-off voltage applied at gate contact 218,thereby creating a current shunting, low impedance conduction channel282 coupling first subregion 266 and tub region 262. Similarsemiconductor design considerations for the control channel MESFET andJFET of FIGS. 2 and 3 may also be applied in creating a “normally-on” ora “normally-off” conduction channel base upon the doping concentrationand thickness of control layer.

The device of FIGS. 5A and 5B omits the topmost n-type semiconductorlayer used in FIG. 4A. Thus, the p-type anode layer 358 also functionsas control layer 360 and defines the thyristor top surface 311. Anenhancement-mode metal-oxide-semiconductor (enhancement-mode MOSFET)369, having first subregion 366 as a source and tub region 362 as adrain, results from gate contacts 318 and insulative layers 330 beingdeposited over control layer 360 and partially over first subregion 366and tub region 362. Prior to thyristor turn-on, the absence of anexternal applied gate voltage prohibits the creation of an enhancedcarrier region 350 between subregion 366 and tub region 362, therebymaintaining a high impedance path between first subregion 366 and tubregion 362. During thyristor “turn-off”, MOSFET 369 operates under anexternal applied gate voltage to create conductive inversion channel 350beneath insulative layer 330 and within field effect region 380 ofcontrol layer 360, thereby creating a current shunting, low impedanceconduction channel 382 coupling first subregion 366 and tub region 362.A “normally-on” gate structure may also be operated with the structureof FIG. 5B by using an appropriate doping concentration for layer 360,thickness of insulative layer 330 and workfunction for the gate metalcontact 318 such that the threshold gate voltage of MOSFET 369 becomesnegative, essentially resulting in a depletion-mode device.

Referring now to FIGS. 6-9, high-power, field-controlled transistors(FCTs) are disclosed having similar fabrication steps and identical gatevariations as the FTOs of FIGS. 2-5. Fabrication of FCT semiconductorlayers is accomplished in the same manner as for corresponding layers ofthe FTOs, with the following differences. First, since only one devicep-n junction is needed, an n-blocking layer 446 of FIG. 6A isepitaxially grown on buffer layer 444 without an overlying separateepitaxial conduction layer. Second, no optional intermediate layer ispresent since buffer layer 444 and substrate 442 are of the sameconductivity type as the n-blocking layer 446. Third, no on-gate contactis needed since the gate structure performs both the FCT turn-on andturn-off functions.

One additional FCT design consideration, not present in the FTOs, isdepicted in FIG. 6A. In particular, rectangular tub region 462 shouldextend from device surface 411 at least to blocking junction 454, andoptionally only slightly beyond. Further, at low external applied devicevoltages, high impedance, field effect region 480 sustains the devicevoltage. To ensure both proper device operation and proper sustenance ofthe device voltage as the device voltage increases, tub region 462should preferably have a width 490 less than one-half the depletiondepth 492 of depletion region 456 in n-thick blocking layer 446. Thislimitation should be satisfied at all applied device voltages up to andincluding the maximum voltage that can be sustained by field effectregion 480 between subregion 468 and tub region 462. This ensures thatthe depletion edges 493 of adjacent device cells reach each other involume 494, beneath the tub region 462, thereby effectively shieldingtub region 462 and field effect region 480 from further increases inexternal applied voltage and ensuring that any increased device voltageis dropped across blocking junction 454. Tub width 490 should typicallybe less than or about one micrometer (1 μm). An alternative embodimentof tub region 462, further achieving the shielding benefits describedabove, includes a triangular etched tub 462′ as shown in FIG. 6B.Triangular tub 462′ is preferably dry etched using SiO₂ or otherinsulator as an etching mask to remove a triangular portion of controllayer 460 and p source layer 458. Ion implantation, preferably usingnitrogen, is then performed, forming a shallow n-type region 463.

In addition to the depletion region 492 created in n-blocking layer 446,the physical size and doping of tub region 462 is preferably such that psource layer 458 depletes tub region 462 of carriers in the horizontalregion 463 adjacent to the p source layer. This depletion area furtherensures that a high resistance path exists between the top ohmic(source) contact 412 and bottom contact (drain) 416 as viewed along thepath including: the first subregion 466, conductive channel 482 (whichmay be “normally on” or “normally off” as described above), conductivetub region 472 and blocking layer region 494 directly beneath conductivetub region 472.

Field-controlled transistor of FIG. 6A is operated by applying anexternal device voltage between top ohmic contact (transistor source)412 and bottom ohmic contact (transistor drain) 416 and an external gatebias voltage at gate contact 418.

Prior to FCT turn-on, the applied gate bias voltage at gate contact 418causes field effect region 480 in control layer 460 of MESFET 469 to be“pinched off,” as previously described for a normally-off device. Theexternal device voltage should be of proper magnitude to operate thetransistor without exceeding the transistor breakdown voltage. As withthe FTOs of FIGS. 2-5, most of the applied device voltage is sustainedacross reverse-biased blocking junction 454 once the depletion region456 in volume 494 beneath tub 462 is large enough to shield tub region462 and field effect region 480 as described above. As with controllayer 460, the doping concentrations and thicknesses of blocking layer446 and source layer 458 affect the maximum sustainable applied devicevoltage and should be fabricated to achieve proper transistor operation.

To turn on the FCT of FIG. 6A, an appropriate potential is applied toMESFET 469 at gate contact 418. In response to the applied gatepotential, the conductive tub region 463 becomes undepleted. Morespecifically, this applied potential creates conduction channel 482which electrically connects first subregion 466 and tub region 462 aspreviously described. Electrons from subregion 466 flow along conductionchannel 482 to tub region 462 and into drain region 416. The tub region463 is flooded with electrons and becomes undepleted. As the currentthrough tub 462 increases, a conical current spreading takes placebeneath tub 462 whereby the injected current through tub 462 spreadslaterally, thereby increasing the current density within the depletionregion in blocking layer 446 in the region laterally adjacent toconductive tubs 462. As the current density increases, the reverse biasvoltage across blocking p-n junction 454 decreases resulting in theturn-on of the field-controlled transistor.

The FCT of FIG. 6A can be turned off by applying an appropriate externalgate voltage at gate contact 418 of MESFET 469 to cause field effectregion 480 to be completely “pinched-off” as described above. Inresponse to the selectively applied gate voltage, the tub region 463becomes depleted. More specifically, removal of conduction channel 482prevents the transport of electrons through tub region 462 and permitsthe depletion layer 458 within blocking layer 446 to be reestablished.The device of FIG. 6A is known as a unipolar device since only onecarrier type, i.e. electrons, are involved in the operation of thedevice.

The operative mechanisms employed by the different gate structures 469,479 489 and 499 of FIGS. 6-9 are identical to those of the FTO devicesof FIGS. 2-5 given the differences in the above-described, overalldevice operation for the FCT. Gate structure 469 of FIG. 6A comprises aSchottky gate (MESFET). Gate structure 479 of FIG. 7 comprises a p-njunction gate (JFET). Gate structures 489 and 499 of FIGS. 7 and 8comprise depletion-mode and enhancement-mode NMOS gates (DMOSFET andEMOSFET). The alternative embodiment of FIG. 6B may also be used for thetub regions of FIGS. 7-9.

FIG. 6C represents an alternative embodiment of top conductive region464 beneath top ohmic contact 412 in FIG. 6A. An n+ implantation is usedto create top conductive region 500 without a p+ subregion. Fullelectrical contact of top ohmic contact 412 with the ion implanted n+region 500 forms the source of the FCT. The alternative embodiment ofFIG. 6C can be properly employed in the devices of FIGS. 6A, 7 and 8.The alternative embodiment of FIG. 6C should not be used with thesemiconductor device of FIG. 9, since p+ subregion 492 must be presentto electrically connect top ohmic contact 490 to control layer 558 andeliminate any MOSFET body bias effect due to the floating voltage ofcontrol layer 558.

Referring now to FIGS. 10-13, high-power, field-gated bipolartransistors (FGBTs) are disclosed having similar fabrication steps andidentical gate variations as the FCTs of FIGS. 6-9. In general, the FGBTof FIG. 10 consists of two p-n junctions, lower p-n junction 648 andblocking p-n junction 654, with device turn-on and turn-off effectedthrough a single gate contact 618. Fabrication of FGBT semiconductorlayers is accomplished in the same manner as for corresponding layers ofthe FCTs, with the following difference. Device fabrication begins witha p+ substrate 642 followed by epitaxial growth of p+ buffer layer 644.Optional intermediate layer 650 is included if an asymmetrical device isdesired. In all other relevant respects, the fabrication of the FGBTs ofFIGS. 10-13 are identical to the corresponding FCTs of FIGS. 6-9.

The operation of the FGBTs of FIGS. 10-13 is similar to that of the FCTsof FIGS. 6-9. More specifically, in response to the selectively appliedgate voltage to the field effect region, the tub region becomes depletedand undepleted in response to the gate voltage, causing the FGBTs ofFIGS. 10-13 to turn off and on, respectively.

FIG. 6B represents an alternative embodiment of the tub regions of FIGS.10-13, and FIG. 6C represents an alternative embodiment of the topconductive region of FIGS. 10, 11 and 12 for the same reasons describedabove.

In another embodiment of the FTO thyristor as shown in FIG. 14A, theanode layer is replaced with a semi-insulating (SI) region 758 at leaston both sides of the p+ sub region 768. In a preferred fabricationmethod, region 758 is converted from an n-type semiconductor into asemi-insulating layer through ion implantation, for example by ionimplanting vanadium in the case of SiC devices. P+ sub region 768 isformed by ion implantation using Al or B or co-implantation of C witheither Al or B. P+ sub region 768 extends through the n-type controllayer 760 and at least to the n-layer 752. The remaining arrangement ofthe structure and operation of device 740 is identical to that of theFTO thyristor shown in FIG. 2A. Since the p-type anode layer is replacedwith semi-insulating layer 758, upper p-n junction 759 is restricted tothe region beneath p+ subregion 768, and the control p-n junctionbeneath the n-type control layer 760 is eliminated.

The inclusion of semi-insulating region 758 in FIG. 14A is used toprevent parasitic currents which otherwise exist in device 40 of FIG.2A. In FIG. 2A, gate 18, forming a Schottky contact with control layer60 of MESFET 69, along with underlying n-type control layer 60 andp-type anode layer 58 effectively act like a “p”−n-p transistor, where“p” denotes a Schottky contact metal. When FTO thyristor 40 is operatingand MESFET 69 is pinched off to prevent the conduction of currentsthrough the control channel, this “p”−n-p transistor effectively has ann-type base region that is depleted of carriers, i.e. “punched through.”This occurs when Schottky gate 18 is biased to deplete carriers fromcontrol layer 60, thereby providing a high impedance region in fieldeffect region 80, effectively turning off conduction channel 82. In thispinched off condition, the depletion boundary 83 extends to touch p-typeanode layer 58 and the “p” region of gate 18 and the p-type layer 58 areeffectively shorted. In this punch through condition, a large,undesirable parasitic current will be drawn from the gate biasingelement 22 of FIG. 1B via gate 18, through the pinched off region andinto p-type anode layer 58 to maintain the depleted channel condition.This parasitic current not only increases the demand on the gatingcircuitry, but may also cause faulty turn-on of the FTO thyristor. Withthe use of semi-insulating layer 758 shown in FIG. 14A, thispunch-through problem is eliminated because semi-insulating region 758effectively isolates control channel 760 and field effect region 780 bylimiting any significant parasitic current conduction in a directionperpendicular to the top device surface and downwards from Schottky gate718. The semi-insulating layer 858 of the device of FIG. 15, employing aJFET channel region, operates in the same manner with the Schottky gate“p” region being replaced in function by the p+ ion implanted region860.

The details of metal semiconductor field effect transistor (MESFET) 769are illustrated in FIG. 14B. Specifically, the voltage applied to thegate 718 should be such that the MESFET channel is created andconducting current only when the FTO thyristor of FIG. 14A is to beturned off. When MESFET 769 is designed to be a normally-off device, aforward voltage pulse is applied to gate 718 only during FTO thyristorturn-off to bypass the anode current through MESFET 769. Alternatively,MESFET 769 may also be designed to be a normally-on device, i.e. aconducting channel exists under gate 718 even before any external gatevoltage is applied. In the case of a normally-on MESFET 769, a reversegate voltage is needed to interrupt the channel of MESFET 769 and toturn on FTO thyristor 740 and maintain it in the “on” state. In eithercase, the FTO thyristor 740 is turned off by applying the necessarypotential to gate 718 to open up the channel of MESFET 769 so as tobypass anode current and turn off FTO thyristor 740.

The FTO thyristor of FIG. 15A is fabricated and operated in a mannersimilar to the device of FIG. 14A, with the differences being in thefabrication and operation of the gate contact 818. In the device of FIG.15A, a p+ ion implanted region 800 is created and extends into thecontrol layer 860 from top device surface 811 between first subregion866 and tub region 862. Further, the metal contact between gate contact818 and p+ region 800 is an ohmic contact whereas the contact in FIG.14A between gate contact 718 and the n-type layer 760 is a Schottkybarrier contact. As with the FTO device of FIG. 3B, the p+ region 800,n+ sub region 866, n+ tub region 862, and conduction channel 882 form ajunction field effect transistor (JFET) 869. Just as MESFET 769 of FIG.14B, can be either normally-off or normally-on, JFET 869 can also beeither normally-off or normally-on. As with the device of FIG. 14, thereplacement of the p-type anode layer with semi-insulating layer 858results in the upper p-n junction 859 being restricted to the regionbeneath p-type subregion 868 and the control p-n junction beneath n-typecontrol layer 860 is eliminated.

JFET 869 of FIG. 15B operates in the same manner as JFET 169 of FIG. 3B.FIG. 15B shows the detail of JFET 869 which is constructed and operatedidentically to JFET 169 of FIG. 3B. In particular, for a normally-onJFET, a reverse bias voltage applied to the gate contact 818 causes thedepletion boundary 883 to extend towards semi-insulating region 858 andturns off JFET 869 through pinch off. This, in turn, allows the turn-onof the FTO thyristor through p+ subregion 868 and n-type conductionlayer 852, essentially a p-n diode, by applying a turn-on current to theon-gate contact 820. Semi-insulating region 858 serves the same purposesin reducing parasitic currents as discussed with respect tosemi-insulating region 758 of FIG. 14A above. For a normally-off JFET,no gate bias is needed as the pinch-off condition is present without agate bias voltage. In comparison to MESFET 769 of FIG. 14B, JFET 869enables the device of FIG. 15 to operate at higher temperatures becauseof the well-known, superior temperature tolerance of JFETs in comparisonto MESFETs. When implemented using SiC semiconductor, the device of FIG.15A can be operated at ambient temperatures of greater than 500 degreesCelsius. Further, the device of FIG. 15A has a higher reliability than asimilarly fabricated metal-oxide-field-effect transistor (MOSFET) sinceoxides and other insulator gate dielectrics are known to degradesemiconductor device reliability at high temperatures.

The device shown in FIG. 16 is the device analogous to the field gatedbipolar transistor (FGBT) device of FIG. 10 with the difference being inthe inclusion of semi-insulating layer 1663. In the FGBT device of FIG.16, semi-insulating region 1663 is introduced on both sides of p+subregion 1668 by converting parts of p-type layer 1658 through ionimplantation, for example by ion implanting vanadium in the case of SiCdevices, or by directly converting parts of n-type layer 1660 or 1646.Semi-insulating region 1663 provides the same advantages with respect tothe reduction of parasitic currents as semi-insulating region 758 in thedevice of FIG. 14A. In particular, semi-insulating region 1663 preventsparasitic current conduction from Schottky gate contact 1618 throughn-type layer 1660 and p-type layer 1658 to p+ sub region 1668. In thedevice of FIG. 16, n-type sub regions 1662 do not have to be ionimplanted to form a heavily doped tub region as in the device of FIG.10, but instead may be doped with a concentration the same as either then-blocking layer 1646 or the n-type control layer 1660. Consequently,this means that the n-type sub region 1662 can be part of theepitaxially grown blocking layer 1646 or the epitaxially grown controllayer 1660 when p-type layer 1658 is formed. For example, p-type layer1658 may be formed by ion implantation of B or Al or C plus either B orAl, thereby converting n-type layer 1646 into p-type layer 1658. In FIG.16, n+ subregion 1666, n tub region 1662, control layer (controlchannel) 1660, and gate 1618 form a MESFET which can be eithernormally-off or normally-on. In response to a selectively applied gatevoltage, the tub region 1662 is alternatively depleted and undepleted,causing the FGBT to turn off and on, respectively. More specifically,for a normally-off MESFET, a gate voltage is applied to gate 1618 toreduce the depletion width and create a conducting channel so thatelectrons from n+ region 1666 flood the tub region, which leads to theturn-on of the device of FIG. 16. For a normally-on MESFET, a gatevoltage is applied to gate 1618 to extend the depletion width andpinch-off the conducting channel, causing the tub region to be depleted,and leading to the turn-off of the device of FIG. 16. In all otherrespects, the FGBT device of FIG. 16 is fabricated and operated in asimilar manner as the FGBT device of FIG. 10 above. As can be seen inFIG. 16, the control p-n junction has been entirely eliminated in thisdevice as a result of the inclusion of semi-insulating layer 1663. FIG.16B shows an alternative embodiment of MESFET 1669. The recessedSchottley gate 1619 is included to reduce the channel resistance.

The FGBT device of FIG. 17 is fabricated and operated in a mannersimilar to the FGBT device of FIG. 16, with the only difference being inthe fabrication and operation of the p-type region 2600 and gate contact2618. In the device of FIG. 17, a p+ type, region 2600 is created by ionimplantation and extends into control layer 2660 from top device surface2811 between n+ sub region 2666 and n-type sub region 2662. The p+region 2600, n+ sub region 2666, n-type sub region 2662, and controllayer 2660 form either a normally-on or a normally-off junction fieldeffect transistor (JFET) 2669 as in the device of FIG. 11. FIG. 17Bshows an alternative embodiment of JFET 2669. The recessed ohmic metalgate 2619 is included to reduce the channel resistance. Because of themonolithic integration of the JFET 2669 of FIG. 17, as with the deviceof FIG. 15 above, the FGBT of FIG. 17 can be operated at temperaturesgreater than 500 degrees Celsius. Also as with the device of FIG. 15above, the FGBT of FIG. 17 has a higher reliability than a similarlyfabricated metal-oxide-field-effect transistor (MOSFET) since oxides andother insulator gate dielectrics are known to degrade semiconductordevice reliability at high temperatures.

The device of FIG. 18 is a field controlled transistor (FCT) similar tothe device of FIG. 6. This device is fabricated and operated similarlyto the FGBT device of FIG. 16, with the only difference being in the useof substrate 3642. In particular, substrate 3642 of the device of FIG.18 is of the same n-type doping as the control layer 3660, whereas inthe FGBT device of FIG. 16, the substrate 1642 is of the opposite dopingtype as compared to the control layer 1660. In all other respects, theFCT device of FIG. 18 operates in a manner similar to the FCT device ofFIG. 6A as described above. Specifically, the tub region isalternatively depleted and undepleted in response to a selectivelyapplied gate voltage which causes the FCT to switch off and on,respectively. The recessed gate implementation of FIG. 16B can also beused for the device of FIG. 18.

One advantage of the FCT of FIG. 18 is that it operates as a majoritycarrier, unipolar semiconductor device -since no minority carrierinjection or carrier storage occurs in blocking layer 3646. Incomparison, the FGBT device of FIG. 16 is a bipolar device since layers1666 (n+), 1646 (n−) and 1642 (p+) operate as an n+n−p+ diode when theFGBT is in the ON-state. Consequently, the device of FIG. 16 employsminority carrier injection and storage. Thus, the devices of FIGS. 16and 17 have current-voltage characteristics similar to that of thewell-known insulated gate bipolar transistor (IGBT) while avoiding theuse of SiO₂ or other gate dielectric materials. For high temperature andhigh power devices, fabricated from SiC for example, the elimination ofSiO₂ or other gate insulators represents a major advantage due to thewell known reliability concerns of gate insulators at high temperaturescoupled with the low channel mobility present in SiC-based metal oxidesemiconductor field effect transistors (MOSFETs) or metal-insulatorsemiconductor field effect transistors (MISFETs).

The FCT device of FIG. 19 is fabricated and operated similarly to theFGBT device of FIG. 17 with the difference between them being identicalto the differences between the FCT device of FIG. 18 and the FGBT deviceof FIG. 16 mentioned above. The fabrication and operation of the JFET,including the p+ region 4600, is identical to that mentioned in thedescription of the FGBT device of FIG. 17 above. As with the FGBT deviceof FIG. 17, the monolithic integration of the JFET in the FCT device ofFIG. 19 permits highly reliable operation of the FCT at temperaturesgreater than 500 degrees Celsius. The recessed gate implementation ofFIG. 17B can also be used for the device of FIG. 19.

While the particular embodiments of the invention have been shown anddescribed, it will be obvious to those skilled in the art that thespecific terms and figures are employed in a generic and descriptivesense only and not for the purposes of limiting or reducing the scope ofthe broader inventive aspects herein. The monolithic power semiconductorstructures and methods of operation of the present invention areapplicable to a broad range of semiconductor devices which can befabricated from a variety of semiconductor materials. By disclosing thepreferred embodiments of the present invention above, it is not intendedto limit or reduce the scope of coverage for the general applicabilityof the present invention to specific devices or semiconductor materials.Moreover, the disclosed embodiments employ sample semiconductorconductivity types for each layer (i.e. p-type or n-type) along withcorresponding, appropriate device and gate biasing voltages. Persons ofskill in the art will easily recognize the substitution of n-type forp-type and vice-versa along with appropriate corresponding changes indevice and biasing voltage polarities to correctly operate the devices.Furthermore, while a single vertical power device per wafer isdisclosed, other structures yielding multiple devices per wafer, such asa horizontal devices, may also be constructed according to the teachingsof the present invention.

This application claims the benefit of U.S. application Ser. No.09/095,481, filed Jun. 10, 1998, the disclosure of which is herebyincorporated by reference herein.

INDUSTRIAL APPLICABILITY

These field turn-off devices have wide-spread applications in the entirefield of power electronics, such as electric motor control, powertrainsfor electric vehicles, power conditioning, general electric utilitycontrol, nuclear power systems.

What is claimed is:
 1. A semiconductor device comprising: (a) asemiconductor structure having top and bottom surfaces, said structureincluding a plurality of semiconductor layers defining a blocking p-njunction remote from both said surfaces, said structure including acontrol layer defining the top surface of the structure; a topconductive region extending from said top surface; a conductive tubregion spaced apart from said top conductive region and extending fromsaid top surface toward said blocking p-n junction at least through saidcontrol layer, said control layer including a field effect regiondisposed between said top conductive region and said conductive tubregion; (b) a top ohmic contact in contact with said top surface at saidtop conductive region; (c) a bottom ohmic contact in contact with saidsemiconductor structure below said blocking p-n junction, saidsemiconductor layers being arranged so that when a potential issustained between said top and bottom ohmic contacts, a major portion ofsaid potential appears across said blocking p-n junction thereby formingdepletion regions about said blocking p-n junction, and (d) a gatecontact overlying said field effect region, whereby conductivity of saidfield effect region can be selectively controlled by a controllingpotential on said gate contact to create and interrupt a conductivechannel within said control layer, said top conductive region and saidconductive tub region being coupled and decoupled by said conductivechannel, said conductive tub region extending downwardly to the vicinityof said blocking p-n junction so that a least resistive current pathincluding said top conductive region, said conductive channel and saidconductive tub region is created between said top ohmic contact and saidblocking p-n junction when said conductive channel is created.
 2. Thesemiconductor device of claim 1 further comprising a control p-njunction disposed above said blocking p-n junction and remote from saidtop surface, said gate contact forming a Schottky contact such that saidgate contact, said field effect region, said top conductive region andsaid conductive tub region constitute a MESFET.
 3. The semiconductordevice of claim 1 further comprising a control p-n junction disposedabove said blocking p-n junction and remote from said top surface, saidfield effect region having a gate conductive region extending from saidtop surface under said gate contact toward said control p-n junctionsuch that said gate contact, said gate conductive region, said fieldeffect region, said top conductive region and said conductive tub regionconstitute a JFET.
 4. The semiconductor device of claim 1 furthercomprising a control p-n junction disposed above said blocking p-njunction and remote from said top surface, said gate contact includingan insulative layer on said top surface and a conductive contact on saidinsulative layer such that said gate contact, said field effect region,said top conductive region and said conductive tub region constitute aMOSFET.
 5. The semiconductor device of claim 1 in which said topconductive region includes a first subregion of same semiconductor typeas said control layer and extending to a first depth from said topsurface, a second subregion of opposite semiconductor type from saidcontrol layer extending to a second depth from said top surface anddisposed between said first subregion and said field effect region, bothof said subregions being in contact with said top ohmic contact, saidgate contact including an insulative layer on said top surface and aconductive contact on said insulative layer such that said gate contact,said field effect region, said second subregion of said top conductiveregion and said conductive tub region constitute a MOSFET.
 6. Thesemiconductor device of claim 4 or claim 5 in which said field effectregion includes unimplanted epitaxially grown semiconductor definingsaid top surface in said field effect region, whereby said insulativelayer includes an insulating compound on said unimplanted epitaxiallygrown semiconductor.
 7. The semiconductor device of claim 1 in whichsaid semiconductor device is a field controlled transistor, saidconductive tub region extending at least to said blocking p-n junctionand having a bottom end being disposed in said depletion region of saidblocking p-n junction when said potential is sustained between said topand bottom ohmic contacts, said conductive tub region beingalternatively depleted and undepleted of carriers in response to saidselective controlling potential on said gate contact, whereby saidtransistor switches “off” and “on” respectively.
 8. The semiconductordevice of claim 7 in which said top conductive region includes a firstsubregion of same semiconductor type as said control layer and extendingto a first depth from said top surface; a second subregion of oppositesemiconductor type from said control layer extending to a second depthfrom said top surface and disposed between said first subregion and saidfield effect region, both subregions in contact with said top ohmiccontact, said gate contact including an insulative layer on said topsurface and a conductive contact on said insulative layer such that saidgate contact, said field effect region, said second subregion of saidtop conductive region and said conductive tub region constitute aMOSFET.
 9. The semiconductor device of claim 7 further comprising acontrol p-n junction disposed above said blocking p-n junction andremote from said top surface, said gate contact forming a Schottkycontact such that said gate contact, said field effect region, said topconductive region and said conductive tub region constitute a MESFET.10. The semiconductor device of claim 7 further comprising a control p-njunction disposed above said blocking p-n junction and remote from saidtop surface, said field effect region having a gate conductive regionextending from said top surface under said gate contact toward saidcontrol p-n junction such that said gate contact, said gate conductiveregion, said field effect region, said top conductive region and saidconductive tub region constitute a JFET.
 11. The semiconductor device ofclaim 7 further comprising a control p-n junction disposed above saidblocking p-n junction and remote from said top surface, said gatecontact including an insulative layer on said top surface and aconductive contact on said insulative layer such that said gate contact,said field effect region, said top conductive region and said conductivetub region constitute a MOSFET.
 12. The semiconductor device of claim 1in which said semiconductor device is a field-gated bipolar transistor,said semiconductor structure having a lower p-n junction remote fromsaid top and bottom surfaces and disposed below said blocking p-njunction, said conductive tub region extending at least to said blockingOn junction and having a bottom end being disposed in said depletionregion of said blocking p-n junction when said potential is sustainedbetween said top and bottom ohmic contacts, said conductive tub regionbeing alternatively depleted and undepleted in response to saidselective controlling potential on said gate contact, whereby saidbipolar transistor switches “off” and “on” respectively.
 13. Thesemiconductor device of claim 12 in which said top conductive regionincludes a first subregion of same semiconductor type as said controllayer and extending to a first depth from said top surface, a secondsubregion of opposite semiconductor type from said control layerextending to a second depth from said top surface and disposed betweensaid first subregion and said field effect region, both subregions incontact with said top ohmic contact, said gate contact including aninsulative layer on said top surface and a conductive contact on saidinsulative layer such that said gate contact, said field effect region,said second subregion of said top conductive region and said conductivetub region constitutes a MOSFET.
 14. The semiconductor device of claim13 further comprising a control p-n junction disposed above saidblocking p-n junction and remote from said top surface, said gatecontact forming a Schottky contact such that said gate contact, saidfield effect region, said top conductive region and said conductive tubregion constitute a MESFET.
 15. The semiconductor device of claim 13further comprising a control p-n junction disposed above said blockingp-n junction and remote from said top surface, said field effect regionhaving a gate conductive region extending from said top surface undersaid gate contact toward said control p-n junction such that said gatecontact, said field effect region, said gate conductive region, said topconductive region and said conductive tub region constitute a JFET. 16.The semiconductor device of claim 13 further comprising a control p-njunction disposed above said blocking p-n junction and remote from saidtop surface, said gate contact including an insulative layer on said topsurface and a conductive contact on said insulative layer such that saidgate contact, said field effect region, said top conductive region andsaid conductive tub region constitute a MOSFET.
 17. The semiconductordevice of claim 1 in which said semiconductor device is a field turn-offthyristor; (a) said top conductive region including a first subregionextending to a first depth from said top surface, and a second subregionextending to a second depth from said top surface and disposed betweensaid first subregion and said field effect region, both subregions incontact with said top ohmic contact; (b) said semiconductor structurehaving a lower and an upper p-n junction, both remote from said top andbottom surfaces; said lower p-n junction disposed below said blockingp-n junction, said upper On junction disposed above said blocking p-njunction, said conductive tub region extending at least through saidupper p-n junction; a latch-on gate ohmic contact overlying saidconductive tub region at said top surface, whereby when said conductivechannel is interrupted, current flow through said conductive tub regioncan be selectively controlled by a controlling current applied throughsaid latch-on gate ohmic contact to turn on said upper p-n junction andthereby switch “on” said thyristor; and whereby in an absence of saidcontrolling current on said latch-on gate contact, said controllingpotential on said gate contact can create said conductive channel tobypass said upper p-n junction and thereby switch “off” said thyristor.18. The semiconductor device of claim 17 in which said first subregionis of same semiconductor type as said control layer, said secondsubregion is of opposite semiconductor type from said control layer,said gate contact including an insulative layer on said top surface anda conductive contact on said insulative layer such that said gatecontact, said field effect region, said second subregion of said topconductive region and said conductive tub region constitute a MOSFET.19. The semiconductor device of claim 18 further comprising a controlp-n junction disposed above said upper p-n junction and remote from saidtop surface, said first subregion being of opposite semiconductor typefrom said control layer, said second subregion of same semiconductortype as said control layer, said first depth of said first subregionextending beyond said control p-n junction from said top surface, saidgate contact forming a Schottky contact such that said gate contact,said field effect region, said second subregion of said top conductiveregion and said conductive tub region constitute a MESFET.
 20. Thesemiconductor device of claim 18 further comprising a control p-njunction disposed above said upper p-n junction and remote from said topsurface, said first subregion being of opposite semiconductor type fromsaid control layer, said second subregion of same semiconductor type assaid control layer, said first depth of said first subregion extendingbeyond said control p-n junction from said top surface, said fieldeffect region further comprises a gate conductive region extending fromsaid top surface under said gate contact toward said control p-njunction such that said gate contact, said field effect region, saidgate conductive region, said second subregion of said top conductiveregion and said conductive tub region constitute a JFET.
 21. Thesemiconductor device of claim 18 further comprising a control p-njunction disposed above said upper p-n junction and remote from said topsurface, said first subregion being of opposite semiconductor type fromsaid control layer, said second subregion of same semiconductor type assaid control layer, said first depth of said first subregion extendingbeyond said control p-n junction from said top surface, said gatecontact including an insulative layer on said top surface and aconductive contact on said insulative layer such that said gate contact,said field effect region, said second subregion of said top conductiveregion and said conductive tub region constitute a MOSFET.
 22. Thesemiconductor device of claim 12 or claim 17 in which said semiconductorstructure further comprises a blocking layer of relatively low dopingconcentration disposed below said blocking p-n junction and anenhancement layer of same semiconductor type and relatively higherdoping concentration as said blocking layer disposed above said lowerp-n junction.
 23. The semiconductor device of any one of claims 2, 3, 4,9, 10, 11, 14, 15, or 16 in which said top conductive region includes afirst subregion of opposite semiconductor type from said control layerand extending through said control p-n junction from said top surface,and a second subregion of the same semiconductor type as said controllayer extending to a second depth from said top surface and disposedbetween said first subregion and said field effect region, both of saidsubregions in contact with said top ohmic contact.
 24. The semiconductordevice of claim 1 in which said semiconductor layers are composed of amaterial selected from the group consisting of SiC, Si, Diamond, GaAs,GaN, AlN, AlGaN, InGaN, GaP, AlGaP or AlGaAsP and combinations thereof.25. The semiconductor device of claim 1 in which said semiconductorlayers include a bottom layer, said bottom layer being in contact withsaid bottom ohmic contact and further including a buffer layer forimproving said semiconductor structure quality.
 26. The semiconductordevice of claim 1 in which said semiconductor device has no insulativelayer as part of said gate contact.
 27. The semiconductor device ofclaim 1 further comprising a control p-n junction disposed above saidblocking p-n junction and remote from said top surface, said fieldeffect region including an unimplanted portion of said control layer.28. The semiconductor device of claim 1 further comprising a control p-njunction disposed above said blocking pan junction and remote from saidtop surface; an upper p-n junction disposed between said blocking p-njunction and said control p-n junction.
 29. The semiconductor device ofclaim 1 further comprising a lower p-n junction disposed below saidblocking p-n junction and remote from said bottom surface.
 30. Thesemiconductor device of claim 1 in which said top conductive regionincludes a first subregion of opposite semiconductor type from saidcontrol layer extending to a first depth at least through said controllayer from said top surface; a second subregion of the samesemiconductor type as said control layer extending to a second depth notthrough said control layer from said top surface and disposed betweensaid first subregion and said field effect region, said first and secondsubregions being in contact with said top ohmic contact.
 31. Thesemiconductor device of claim 1 in which said top conductive regionincludes a first subregion of same semiconductor type as said controllayer extending to a first depth not through said control layer fromsaid top surface; a second subregion of opposite semiconductor type fromsaid control layer and extends to a second depth, shallower than saidfirst depth, from said top surface and disposed between said firstsubregion and said field effect region, both subregions being in contactwith said top ohmic contact.
 32. The semiconductor device of claim 1 inwhich said conductive tub region extends at least to said blocking p-njunction and has a bottom end disposed in said depletion region of saidblocking p-n junction when said potential is sustained between said topand bottom ohmic contacts such that said field effect region is shieldedfrom said potential.
 33. The semiconductor device of claim 1 furthercomprising a latch-on gate ohmic contact overlying said conductive tubregion at said top surface.
 34. The semiconductor device of claim 1further comprising a lower and an upper p-n junction, both remote fromsaid top and bottom surfaces, said lower p-n junction disposed belowsaid blocking p-n junction, said upper p-n junction disposed above saidblocking p-n junction, said conductive tub region extending through saidupper p-n junction; a latch-on gate ohmic contact overlaying saidconductive tub region at said top surface, said semiconductor layersbeing of relative conductivity, whereby a latch-on current applied atsaid latch-on gate ohmic contact, flows through said conductive tubregion and laterally beneath said upper p-n junction before traversingsaid upper p-n junction beneath said top ohmic contact.
 35. Thesemiconductor device of claim 1 further comprising a semi-insulatinglayer disposed directly beneath said control layer and said field effectregion; said conductive tub region extending at least through saidsemi-insulating layer, whereby said field effect region within saidcontrol layer is electrically isolated by said semi-insulating layerfrom a semiconductor layer directly beneath said semi-insulating layerin a direction perpendicular to said top surface.
 36. The semiconductordevice of claim 35 wherein said gate contact forms a Schottky contactsuch that said gate contact, said field effect region, said topconductive region and said conductive tub region constitute a MESFET.37. The semiconductor device of claim 35 wherein said field effectregion further includes a gate conductive region extending from said topsurface under said gate contact toward said semi-insulating layer suchthat said gate contact, said gate conductive region, said field effectregion, said top conductive region and said conductive tub regionconstitute a JFET.
 38. The semiconductor device of claim 35 in whichsaid semiconductor device is a field controlled transistor, saidconductive tub region extending at least to said blocking p-n junctionand having a bottom end being disposed in said depletion region of saidblocking p-n junction when said potential is sustained between said topand bottom ohmic contacts, said conductive tub region beingalternatively depleted and undepleted in response to said selectivecontrolling potential on said gate contact, whereby said transistorswitches “off” and “on” respectively.
 39. The semiconductor device ofclaim 38 in which said conductive tub comprises a part of a blockinglayer defining a lower semiconductor layer of said blocking p-njunction.
 40. The semiconductor device of claim 38 in which saidconductive tub comprises a part of said control layer.
 41. Thesemiconductor device of claim 38 in which said conductive tub comprisesan ion implanted region extending from said top surface.
 42. Thesemiconductor device of claim 38 in which said gate contact forms aSchottky contact such that said gate contact, said field effect region,said top conductive region and said conductive tub region constitute aMESFET.
 43. The semiconductor device of claim 38 in which said fieldeffect region further comprises a gate conductive region extending fromsaid top surface under said gate contact toward said semi-insulatinglayer such that said gate contact, said gate conductive region, saidfield effect region, said top conductive region and said conductive tubregion constitute a JFET.
 44. The semiconductor device of claim 35 inwhich said semiconductor device is a field-gated bipolar transistor,said semiconductor structure having a lower p-n junction remote fromsaid top and bottom surfaces and disposed below said blocking p-njunction, said conductive tub region extending at least to said blockingp-n junction and having a bottom end being disposed in said depletionregion of said blocking p-n junction when said potential is sustainedbetween said top and bottom ohmic contacts, said conductive tub regionbeing alternatively depleted and undepleted in response to saidselective controlling potential on said gate contact, whereby saidbipolar transistor switches “off” and “on” respectively.
 45. Thesemiconductor device of claim 44 in which said conductive tub comprisesa part of a blocking layer defining a lower semiconductor layer of saidblocking p-n junction.
 46. The semiconductor device of claim 44 in whichsaid conductive tub comprises a part of said control layer.
 47. Thesemiconductor device of claim 44 in which said conductive tub comprisesan ion implanted region extending from said top surface.
 48. Thesemiconductor device of claim 44 in which said gate contact forms aSchottky contact such that said gate contact, said field effect region,said top conductive region and said conductive tub region constitute aMESFET.
 49. The semiconductor device of claim 44 in which said fieldeffect region further comprises a gate conductive region extending fromsaid top surface under said gate contact toward said semi-insulatinglayer such that said gate contact, said gate conductive region, saidfield effect region, said top conductive region and said conductive tubregion constitute a JFET.
 50. The semiconductor device of claim 35 inwhich said semiconductor device is a field turn-off thyristor; (a) saidtop conductive region including a first subregion extending to a firstdepth and at least through said semi-insulating layer from said topsurface, and a second subregion extending to a second depth from saidtop surface, said second subregion disposed between said first subregionand said field effect region, both subregions in contact with said topohmic contact; (b) said semiconductor structure having a lower and anupper p-n junction, both remote from said top and bottom surfaces; saidlower p-n junction disposed below said blocking p-n junction, said upperp-n junction disposed above said blocking p-n junction and beneath saidfirst subregion; a latch-on gate ohmic contact overlying said conductivetub region at said top surface, whereby when said conductive channel isinterrupted, current flow through said conductive tub region can beselectively controlled by a controlling current applied through saidlatch-on gate ohmic contact to turn on said upper p-n junction andthereby switch “on” said thyristor; and whereby in an absence of saidcontrolling current on said latch-on gate contact, said controllingpotential on said gate contact can create said conductive channel tobypass said upper p-n junction and thereby switch “off” said thyristor.51. The semiconductor device of claim 50 wherein said first subregion isof opposite semiconductor type from said control layer and said secondsubregion is of same semiconductor type as said control layer.
 52. Thesemiconductor device of claim 50 in which said gate contact forms aSchottky contact such that said gate contact, said field effect region,said second subregion of said top conductive region and said conductivetub region constitute a MESFET.
 53. The semiconductor device of claim 50in which said field effect region further comprises a gate conductiveregion extending from said top surface under said gate contact towardsaid semi-insulating layer such that said gate contact, said fieldeffect region, said gate conductive region, said second subregion ofsaid top conductive region and said conductive tub region constitute aJFET.
 54. The semiconductor device of claim 50 in which saidsemiconductor structure further comprises a blocking layer of relativelylow doping concentration disposed below said blocking p-n junction andan enhancement layer of same semiconductor type and relatively higherdoping concentration as said blocking layer disposed above said lowerp-n junction.
 55. The semiconductor device of any one of claims 36, 37,42, 43, 48, 49, 52 or 53 in which said top conductive region includes afirst subregion of opposite semiconductor type from said control layerand extending to a first depth at least through said control layer fromsaid top surface, and a second subregion of the same semiconductor typeas said control layer and extending to a second depth from said topsurface and disposed between said first subregion and said field effectregion, both of said subregions in contact with said top ohmic contact.56. The semiconductor device of claim 35 in which said semiconductorlayers are composed of a material selected from the group consisting ofSiC, Si, Diamond, GaAs, GaN, AlN, AlGaN, InGaN, GaP, AlGaP or AlGaAsPand combinations thereof.
 57. The semiconductor device of claim 35 inwhich said semiconductor layers include a bottom layer, said bottomlayer being in contact with said bottom ohmic contact and furtherincluding a buffer layer for improving said semiconductor structurequality.
 58. The semiconductor device of claim 35 in which saidsemiconductor device has no insulative layer as part of said gatecontact.
 59. The semiconductor device of claim 35 further comprising alower p-n junction disposed below said blocking p-n junction and remotefrom said bottom surface.
 60. The semiconductor device of claim 55further comprising an upper p-n junction disposed above said blockingp-n junction, below said first subregion and remote from said topsurface.
 61. The semiconductor device of claim 35 in which saidconductive tub region extends at least to said blocking p-n junction andhas a bottom end disposed in said depletion region of said blocking p-njunction when said potential is sustained between said top and bottomohmic contacts such that said field effect region is shielded from saidpotential.
 62. The semiconductor device of claim 35 further comprising alatch-on gate ohmic contact overlying said conductive tub region at saidtop surface.
 63. The semiconductor device of claim 35 further comprisinga lower and an upper p-n junction, both remote from said top and bottomsurfaces, said lower p-n junction disposed below said blocking p-njunction, said upper p-n junction disposed above said blocking Anjunction, said conductive tub region extending to a distance furtherfrom said top surface than said upper p-n junction; a latch-on gateohmic contact overlaying said conductive tub region at said top surface,said semiconductor layers being of relative conductivity, whereby alatch-on current applied at said latch-on gate ohmic contact, flowsthrough said conductive tub region and laterally beneath said upper p-njunction before traversing said upper p-n junction beneath said topohmic contact.
 64. The method of operating a semiconductor device havinga plurality of semiconductor layers, a top and bottom surface andincluding a control layer defining the top layer of the device, saidmethod comprising the steps of: (a) applying a voltage between a top anda bottom ohmic contact of said semiconductor device; (b) sustaining saidvoltage across a blocking p-n junction defined by said semiconductorlayers and remote from said top and bottom surfaces; (c) selectivelycreating or interrupting a conductive channel in said control layerbetween a top conductive region, disposed below said top ohmic contact,and a tub conductive region, spaced apart from said top conductiveregion and extending at least to said blocking p-n junction, by applyinga control potential to a gate contact disposed over said control layerso as to cause a least resistive path including said top conductiveregion, said conductive channel and said conductive tub region to becreated between said top ohmic contact and said blocking p-n junctionwhen said conductive channel is created.
 65. The method of operating asemiconductor device having a plurality of semiconductor layers, a topand bottom surface and including a control layer defining the top layerof the device, said method comprising the steps of: (a) applying avoltage between a top and a bottom ohmic contact of said semiconductordevice; (b) sustaining said voltage across a blocking p-n junctiondefined by said semiconductor layers and remote from said top and bottomsurfaces; (c) selectively applying a control current to a latch-on gatecontact disposed over a tub conductive region, said tub conductiveregion extending through an upper p-n junction defined by saidsemiconductor layers and remote from said top and bottom surfaces, saidupper p-n junction being disposed above said blocking p-n junction andbeing selectively turned on when said control current is selectivelyapplied to said latch-on gate; (d) selectively creating or interruptinga conductive channel in said control layer between a top conductiveregion, disposed below said top ohmic contact, and a tub conductiveregion, spaced apart from said top conductive region and extendingthrough said upper p-n junction, by applying a control potential to agate contact disposed over said control layer so as to selectivelyshort-circuit said upper p-n junction when said conductive channel iscreated thereby turning off said thyristor semiconductor device.